PARTNER SHORT DESCRIPTION
Politecnico di Milano (PDM) is one of the largest Italian engineering universities. In Italy, the term “Politecnico” means a state university consisting only of study programmes in Engineering and Architecture. The Politecnico di Milano is nowadays organized in 17 departments and a network of 9 Schools of Engineering, Architecture and Industrial Design spread over 7 campuses over the Lombardy region with a central administration and management located in Milan. The 9 schools are devoted to education whereas the 17 departments are devoted to research. The number of students enrolled in all campuses is approximately 40,000, which makes the Politecnico di Milano the largest institution in Italy for Engineering, Architecture and Industrial Design. The project will involve personnel of the System Architectures group of the Computer Science and Engineering section of the Dipartimento di Elettronica Informazione e Bioingegneria consists of 4 fullprofessors, 12 associate professors, 8 assistant professors, 24 Ph.D. students and 17 research assistants. The group of System Architectures is active on several research topics, covering both foundational and application-driven aspects. A short list is the following: Security, Performance Evaluation, Dependability, Electronic Design Automation, Processor and Multiprocessor Architectures, Operating Systems, Embedded Systems, Computational Intelligence, Wireless Sensor Networks, Enterprise Digital Infrastructure.
Christian Pilato is a Tenure-Track Assistant Professor at Politecnico di Milano. He was a Post-doc Research Scientist at Columbia University (2013-2016) and at the ALaRI Institute of the Università della Svizzera italiana (2016-2018). He was also a Visiting Researcher at New York University, Delft University of Technology, and Chalmers University of Technology. He has a Ph.D. in Information Technology from Politecnico di Milano (2011). His research interests focus on the design, optimization, and prototyping of heterogeneous system-on-chip architectures and reconfigurable systems, with emphasis on memory and security aspects. Starting from October 2020, he is the Scientific Coordinator of the H2020 EVEREST project. He served as program chair of EUC 2014 and is currently serving in the program committees of many conferences on EDA, CAD, embedded systems, and reconfigurable architectures (DAC, ICCAD, DATE, CASES, FPL, ICCD, etc.) He is a Senior Member of IEEE and ACM, and a Member of HiPEAC.
Gianluca Palermo, received the M.S degree in Electronic Engineering, in 2002, and the Ph.D degree in Computer Engineering, in 2006, from Politecnico di Milano. He is currently an Associate Professor with tenure at Department of Electronics, Information and Bioengineering in the same University. Previously, he was consultant engineer in the Low Power Design Group of AST -STMicroelectronics (Agrate, Italy) working on network on-chip and research associate at the Advanced Learning and Research Institute (ALaRI) of the Universita’ della Svizzera Italiana (Lugano, Switzerland). His research interests include design methodologies and architectures for Embedded and High Performance Computing systems, focusing on multi/many-cores architectures, and application autotuning. He participated to more than 10 international projects acting also as PI for the local unit, project technical manager and WPLeader. Since 2003, he published over 140 peer-reviewed papers including top-level conferences and journals ( >3300 total citations and h-index of 31 according to Google Scholar). He is ACM, HiPEAC and EuroLab4HPC member, IEEE senior member and PoliMi representative within EIT Digital.
Fabrizio Ferrandi is an Associate Professor in the Dipartimento di elettronica, Informazione e Bioingegneria of the Politecnico di Milano. He received the Laurea (cum laude) degree in electronic engineering and the Ph.D. degree in information and automation engineering computer engineering) from the Politecnico di Milano, Milan, Italy, in 1992 and 1997, respectively. The Ph.D. thesis on a Methodology for supporting the Design of Testable Digital Systems has received the Chorafas Foundation prize (1997). He joined the faculty of Politecnico di Milano in 1999 as “Ricercatore” and later in 2002 as Associate Professor with the Dipartimento di Elettronica, Informazione e Bioingegneria. He has published over 140 peer-reviewed papers in international journals, books, and proceedings of international congresses. According to Google Scholar, he collected more than 2900 citations reaching an h-index of 28. He served in several technical and organizing committees in international conferences and workshops, such as DAC, DATE, FPL, CODES-ISSS, ASP-DAC, Computing Frontier, ISIS, SAMOS, NAS, GVLSI, VIPES, ARCS andReConFig. Fabrizio Ferrandi is a member of the IEEE Computer Society, the Test Technology Technical Committee, HiPEAC Network of Excellence for High-Performance and Embedded Architecture and Compilation, and the European Design and Automation Association.He is one of the maintainers of the PandA/Bambu high-level synthesis tool. His current research interests include synthesis, verification, simulation, and testing of digital circuits and systems. He has managed and worked on several ESA/EU funded projects.
Stephanie Soldavini is a PhD student in the Department of Electronics, Informatics and Bioengineering at Politecnicodi Milano. She received her Bachelors and Masters of Science in Computer Engineering from Rochester Institute of Technology in the United States in 2019. Her masters thesis was on reduced-graph based optimizations for scheduling in high-level synthesis. Her research focuses on automatic hardware generation with a focus on memory aspects.
Roberto Rocco is a Research fellow in the Department of Electronics, Informatics, and Bioengineering at Politecnico di Milano. He received his Bachelor and Master of Science in Computer Science and Engineering from Politecnico di Milano in 2020. He has been a PRACE Summer-Of-HPC intern at EPCC Edinburgh working on Fault Tolerance with Persistent Memory. His research interests are on fault tolerance for HPC (MPI-based) applications and optimization of adaptive applications in a heterogeneous (fog/edge) environment.
PDM will be the technical coordinator of the project, working on the hardware/software compilation framework, based on the previous experience on hardware design and high-level synthesis, on design space exploration, and on dynamic auto-tuning. Due to its technical coordination role, PDM will also lead WP6, which includes the development of the applications and the target platforms, and the evaluation of the results with the integrated EVEREST design environment.